1. Field of the Invention
The present invention relates to semiconductor varactors and, more particularly, to a varactor and a method of forming a varactor with an increased linear tuning range.
2. Description of the Related Art
A varactor is a semiconductor device that has a voltage-controlled capacitance. As a result, the capacitance across the device varies as the voltage across the device varies. Varactors are commonly used in the voltage-controlled oscillator (VCO) circuits of phase-locked loops (PLLs) which, in turn, are commonly used in high-frequency applications, such as with cellular phones.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional NMOS varactor 100. As shown in FIG. 1, varactor 100, which is formed in a p− substrate 110, includes a n− well 112 that is formed in substrate 110, and an n+ diffusion region 114 which is formed in n− well 112. N− well 112, in turn, is defined to have a lower-plate region 116 that adjoins n+ diffusion region 114. In addition, varactor 100 also includes a layer of gate oxide 120 that is formed on n− well 112 over lower-plate region 116, and an upper-plate gate 122 that is formed on gate oxide layer 120.
FIG. 2 shows a graph 200 that illustrates the operation of varactor 100. Graph 200 utilizes a line CCONVENTIONAL to identify the capacitance (C) across varactor 100 for a voltage V across varactor 100. As shown in FIG. 2, when the voltage V across varactor 100 ranges from a negative value to a positive value, the capacitance C across varactor 100 increases. For example, when ground is applied to n+ diffusion region 114 and a voltage ranging from −0.5V to +0.7 is applied to gate 122, the capacitance C increases from approximately 7.7×10−16 farads to approximately 1.7×10−15 farads.
In addition, as further shown in FIG. 2, varactor 100 also has a substantially linear region of operation. For example, when ground is applied to n+ diffusion region 114 and a voltage ranging from −0.25V to +0.25V is applied to gate 122, the capacitance C substantially linearly increases from approximately 9.0×10−16 farads to approximately 1.5×10−15 farads as shown by line CCONVENTIONAL.
FIGS. 3A–3B shows cross-sectional diagrams that illustrate the operation of varactor 100 at the linear endpoints. As shown in FIG. 3A, when ground is applied to n+ diffusion region 114 and the lower linear endpoint of −0.25V is applied to upper-plate gate 118, the negative voltage causes a depletion region 310 to be formed in the lower-plate region 116 of n− well 112. The capacitance of varactor 100 in this condition is defined by the thickness of gate oxide layer 120 and the charge on lower-plate region 116 which, in turn, is defined by depletion region 310.
By contrast, as shown in FIG. 3B, when ground is applied to n+ diffusion region 114 and the upper linear endpoint of +0.25V is applied to upper-plate gate 118, the positive voltage causes a negative charge 312 to collect (or accumulate) in the lower-plate region 116 of n− well 112. Thus, as shown in FIGS. 3A and 3B, the capacitance of varactor 100 varies with the voltage across varactor 100 because as the voltage on gate 122 is varied, the charge level present in the lower-plate region 116 of n− well 112 also varies.
One of the advantages of varactor 100 is that varactor 100 can easily be integrated into a standard CMOS or BiCMOS fabrication process. N− well 112 can be formed at the same time that the wells for the PMOS transistors are formed, while n+ diffusion region 114 can be formed at the same time that the source and drain regions for the NMOS transistors are formed. In addition, gate oxide layer 120 and gate 122 can be formed at the same time that the oxide layer and MOS gates are formed.
One of the disadvantages of varactor 100 is that varactor 100 provides a relatively small linear tuning range, ranging only from approximately 9.0×10−16 farads to approximately 1.5×10−15 farads. If a greater or lesser amount of capacitance is required, a more complicated structure is required. As a result, there is a need for a varactor with a larger linear tuning range that remains easily integratable into a standard CMOS or BiCMOS fabrication process.